1. Field of the Invention
The invention relates generally to a flash memory device. More particularly to, the invention is concerned with a flash memory device capable of reducing the chip size and improving the program speed of a selected cell, by applying a given voltage to a source of a not-selected cell in order to increase the threshold voltage of the not-selected cell during the selected cell is programmed, and compensating for reduction in the threshold voltage of the not-selected cell due to a drain coupling depending on the drain voltage supplied to bit lines of the selected cell
2. Description of the Prior Art
A conventional flash memory device includes a NOR-type flash memory cell array 1, a decoder unit 2 for controlling the word lines of the cell, and a multiplexer 3 for controlling the bit lines and the source lines of the cell, as shown in FIG. 1A.
The decoder unit 2 consists of a plurality of unit circuit units 21 through 2n depending on inputted pre-decoding signals XPREA and XPREB, which is shown in FIG. 1B. Each of the unit circuit elements is supplied with a first supply power voltage VPPX being a positive high voltage, a reset signal XRST, and a second supply power voltage VEEX being a negative high voltage. For convenience, the construction of the decoder unit in FIG. 1A is substituted with a circuit construction for receiving the first pre-decoding signal XPREA1 as an input.
A first PMOS transistor P11 driven by the reset signal XRST is connected between the third power supply terminal Vcc and the first node Q11. A first NMOS transistor N11 driven by the first pre-decoding signals XPREA0, a fourth NMOS transistor N14 driven by the second pre-decoding signals XPREB0 and a fifth NMOS transistor N15 driven by a sector signal SECTOR is serially between the first node Q11 and a ground terminal Vss. A second PMOS transistor P12 driven by the potential of the second word line WL1 is connected between the first power supply terminal VPPX and the second node Q12. A third PMOS transistor P13 driven by the potential of the second node Q12 is connected between first power supply terminal VPPX and the second word line WL1. A second NMOS transistor N12 driven by the third power supply terminal Vcc is connected between the first node Q11 and the second node Q12. A third NMOS transistor N13 being a triple NMOS transistor, that is driven by the potential of the first node Q11, is connected between the second word line WL1 and the second power supply terminal VEEX.
Meanwhile, the multiplexer 3 is divided into a portion for controlling bit lines and a portion for controlling source lines of each of the cells. The multiplexer 3 for controlling the source lines includes a NMOS transistor connected between the source line and the ground terminal Vss. Each of the NMOS transistors is driven by a source control signal SOCTRL.
A method of programming a conventional flash memory device mentioned above will be now described by reference to the operating timing chart in FIG. 2.
If a program command, a program address and a program data are inputted, the reset signal XRST is transited from a LOW state to a HIGH state. On the other hand, the first pre-decoding signal XPREA1, the second pre-decoding signals XPREB0 and the sector signal SECTOR, which are selected by the program address, are transited from a LOW state to a HIGH state. Therefore, the first PMOS transistor P11 is turned off by the reset signal XRST of a HIGH state. Also, the fourth and fifth NMOS transistor N14 and N15 are turned on by the second pre-decoding signals XPREB0 and the sector signal SECTOR being a HIGH state. Due to this, the potential of the first node Q11 is maintained to be a LOW state. The third NMOS transistor N13 is turned off by the potential of the first node Q11 being a LOW state. Meanwhile, as the second node Q12 is connected through the first node Q11 and the second NMOS transistor N12, they are transited to a LOW state. The third PMOS transistor P13 is turned off by the potential of the second node Q12 being a LOW state. Therefore, the first supply power voltage VPPX is supplied to the second word line WL1. As the potential of the second word line WL1 is kept at a high voltage, the second PMOS transistor P12 is turned off. The first supply power voltage VPPX supplied to the second word line WL1 by means of a gate pump is raised to a program voltage (about 9V). At the same time, the bit line selected by the program address is raised from a LOW state to a program voltage by means of the drain pump, so that the program operation for the selected cell A can proceed. At this time, the source lines in all the cells are maintained at a ground potential Vss since the sixth and seventh NMOS transistors N16 and N17 are turned on by the source control signal SOCTRL being a HIGH state.
However, in the conventional flash memory device performing the above program operation, the drain voltage in the cell is increased to 5V being the program voltage, so that the threshold voltage for a not-selected cell is lowered by a coupling. Due to this, the leakage current of the not-selected cell is increased. Therefore, the program current for the selected cell requires about twice of a pure program current of a cell to significantly increase the size of the drain pump for supplying the current to the bit lines in the cell. Also, there is a problem that the drain voltage in an actually selected cell is significantly lowered to degrade the program speed of the cell since the bit line current of the selected cell is increased.
It is therefore an object of the present invention to provide flash memory device capable of reducing the cell current and improving the program speed when a program operation is performed, by controlling the source voltage of the flash memory cell.
In order to accomplish the above object, a flash memory device according to a first embodiment of the present invention is characterized in that it comprises a flash memory cell array; a multiplexer for selecting bit lines of said flash memory cell array; a decoder for selecting word lines of said flash memory cell array depending on the global word line signals, a control signal, local word line signals and pre-decoding signals; an internal voltage generator for generating a given internal voltage; and a source control unit for applying the internal voltage from said internal voltage generator to sources of a not-selected flash memory cell depending on the global word line signals, a sector program signal, a sector coding signal and a readout signal.
Also, a flash memory device according to a second embodiment of the present invention is characterized in that it comprises a flash memory cell array; a multiplexer for selecting bit lines of said flash memory cell array; a decoder for selecting word lines of said flash memory cell array depending on global word line signals a control signal, local word line signals and pre-decoding signals; an internal voltage generator for generating a given internal voltage; and a source control unit for applying an internal voltage from said internal voltage generator to sources of a not-selected flash memory cell depending on a sector program signal and the potential of said word lines.